Calculator system featuring a subroutine register

ABSTRACT

Disclosed is a portable electronic calculator system implemented in LSI semiconductor technology which features subroutine storage. The subroutine storage is combined with keyboard and flag storage and is preferably implemented as a sequentially addressed memory. The system includes a permanent store memory for storing instruction words, which is addressable by the keyboard storage. After addressing the memory according to a location specified in the keyboard storage, an exchange is executed between the keyboard storage and subroutine. Subsequently, another exchange is executed effecting return of the operating program to the location in the memory previously specified. The subroutine register is under control of the instruction memory, and functions only to exchange its contents with that of the keyboard storage.

Cochran et al.

Dec. 2, 1975 CALCULATOR SYSTEM FEATURING A SUBROUTINE REGISTER IRG 1 R DECODE I: DDCODE DMSK COMMUTATOR SELECTOR GATES SEGNI ENT DDCODE FLA FLAG B RIG.

KEYBOARD REG SUBIOUTINE REG Kl/S 7.9

CONT-0L Fun Fun. minor 52 Primary Examiner-David H. Malzahn Attorney, Agent, or FirmHarold Levine; Edward J. Connors, Jr.; Stephen S. Sadacca Disclosed is a portable electronic calculator system implemented in LSI semiconductor technology which features subroutine storagev The subroutine storage is combined with keyboard and flag storage and is preferably implemented as a sequentially addressed memory. The system includes a permanent store memory for storing instruction words, which is addressable by the keyboard storage. After addressing the memory according to a location specified in the keyboard storage, an exchange is executed between the keyboard storage and subroutine. Subsequently, another exchange is executed effecting return of the operating program to the location in the memory previously specified. The subroutine register is under control of the instruction memory, and functions only to exchange its contents with that of the keyboard storage.

ABSTRACT 6 Claims, 81 Drawing Figures CD COR HECTOR SELBC To" GA TES U.S. Patent Dec. 2, 1975 Sheet 1 0f 63 3,924,110

US. Patent Dec. 2, 1975 Sheet 2 of 63 3,924,110

PR OGRAMM ER CHIP Fig. 2

MEMORY STORAGE PRINTER CHIP BUSY

ARITHMETIC CHIP SEG A SEG B 'rTrrrr-r-rrr DRIVERS SEGMENT DIGIT DRIVERS l6 "K" LINES KEYBOARD US. Patent Dec. 2, 1975 Sheet 3 of 63 3,924,110

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U.S. Patent Dec. 2, 1975 Sheet 4 of 63 3,924,110

mm hnHDm QOmHZO m wrmDm HmU DZOU QM t US. Patent Dec. 2, 1975 Sheet 6 of 63 3,924,110

MAE) 9 5b 3 MO Flag Operation I Branch of M1 A11 Mask ll Condition:1 M2 DPT MS M3 DPT 1 MA DPT C I M5 LLSD 1 (me) M6 EXP MSB M7 EXP 1 M8 KEYBOARD OPERATIONS I M9 MANT 9 (mb) M1O wAIT OPERATIONS M11 MLSD 5 M12 MAEX l LSB M13 MLSD 1 8 (ma) .Ml l MMSD 1 J M15 MAEX 1 R0 A N 7 R1 B+N (Rd) R2 C N MSB R3 O+N RA Shift A Relative R5 Shift B Branch (RC) R6 Shift C Address R7 Shift D I R8 A+B R9 CIE 2 RIO C D R11 A+E 1 I R12 JAE Constant A R13 NO-OP (Ra) Rl L C+ Constant LSB R15 RB-Adder (Mask LSD) I J I3 :O:add=shift left 12 =l=sub=shift right LSB FC 21. 1

J MSB Tl=0utput 1/0 I O INCR1 MINT I EQZAHB O I 3 3 l *3 EFFECTIVE F R I1=DECREMENT E (WHOLE INSTRSO- ig-Q TION CYCLE WITH I w ANY DICIT MASK) O 7=A*E a (y LSB US. Patent Dec.2, 1975 Sheet7of63 3,924,110

The following 8 bits effective only if flag operations 7 (fmd) MSB 16 The following 8 bits effective Generate FlagMask only if Keyboard operations when these t hits equal the U encoded State bits =O=SCAN KYBD (NOTE: ENCODED STATE TIMES ARE +2 FROM ACTUAL STATES) A =l=KT (fma) LSB- =O=KS The following 4 bits (flagopa) effective only during flagmask I5 0 KP except I 85 T15 0 TEST FLAG A I 2 2 1 TEST FLAG B 2 SET FLAG A I I 3 SET FLAG B 2 :OZKP (fd) H ZERO FLAG A MSB 5 ZERO FLAG B I I f 1 :O=KO

l 6 INVERT FLAG A 1 a 7 INVERT FLAG B IO 8 EXCH. FLAG A B =O=KN (fb) 9 COMPARE FLAG A R 10 SET FLAG KR 11 ZERO FLAG KR F/g, 12 COPY FLAG B-+A US. Patent Dec. 2, 1975 Sheet9of63 3,924,110

I STATETIME I Fig, 6a

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US. Patent Fig, 80

Dec. 2, 1975 Sheet 12 of 63 3,924,110

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U.S. Patent Dec. 2, 1975 Sheet 15 of 63 3,924,110

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Fig. 8b 4 0mm csks DNE GO ANYDMD 0/5 878 US. Patent Dec. 2, 1975 Sheet 17 0f 63 3,924,110

Sta-d, 

1. In an electronic calculator system implemented on at least one semiconductor chip, having a clock system for providing cycle and sub-cycle timing, instruction memory means for storing instructions, address register means for addressing the instruction memory means, and input means for receiving external commands, ultimately as addresses of the instruction memory means, the improvement comprising: a. keyboard storage means, operatively connected to the input means for storing multi-bit instruction memory addresses and selectively connected to the address register means for transmitting the memory addresses; b. sub-routine storage means, selectively connectable only to the keyboard storage means, for receiving and storing memory addresses, and for selectively transmitting memory addresses back to the keyboard storage means; and c. control means, operatively connected to the address register means, the keyboard storage means, the sub-routine storage means, and to the instruction memory means, responsive to a selected instruction word from the instruction memory means for causing the transfer of the contents of the keyboard storage means to the address register means and to the subroutine storage means and, under the control of a selected instruction word, from the sub-routine storage means to the keyboard storage means.
 2. The calculator system of claim 1 further comprising strobing means, responsive to the clock system for providing a strobe pulse at each sub-cycle time.
 3. The calculator system of claim 2 wherein the keyboard storage means and the sub-routine storage means each coMprise a sequentially addressed memory having digit columns strobed sequentially by the strobe pulse.
 4. The calculator system of claim 3 wherein the sequentially addressed memory has separate input and output lines and has common read/write address lines sequentially strobed by the strobe pulse.
 5. In an electronic calculator system of the type implemented in LSI circuit technology and having an instruction read-only-memory for storing a relatively large number of instruction words and which is addressable through means responsive to programmable storage means, the programmable storage means comprising address register means for addressing the memory and first storage means for storing and communicating externally and internally a multi-bit word, and a sub-routine storage means under control of the instruction read-only-memory for selectively receiving only the word from the first storage means and for selectively re-transferring the word only to the first storage means, the method of addressing the instruction read-only-memory comprising the steps of: a. entering a binary word in the first storage means representing a specific address of the instruction read-only-memory; b. transmitting the representation to the address register means; c. transferring the representation to the sub-routine storage means; d. addressing the instruction read-only-memory with the representation; and e. re-transferring the representation in the sub-routine storage to the first storage means.
 6. The method of addressing an instruction read-only-memory of claim 5, further including, subsequent to the step of re-transferring, the step of sending the representation to the instruction read-only-memory for relocating the operational sequence of the calculator back to the specific instruction read-only-memory location. 